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general description the MAX5800/max5801/max5802 2-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (dacs) include output buffers and an internal reference that is selectable to be 2.048v, 2.500v, or 4.096v. the MAX5800/max5801/max5802 accept a wide supply voltage range of 2.7v to 5.5v with extremely low power (1.5mw) consumption to accommodate most low-voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100k i (typ) load to an external reference. the MAX5800/max5801/max5802 have an i 2 c-compatible, 2-wire interface that operates at clock rates up to 400khz. the dac output is buffered and has a low sup - ply current of less than 250 f a per channel and a low offset error of q 0.5mv (typ). on power-up, the MAX5800/ max5801/max5802 reset the dac outputs to zero, pro - viding additional safety for applications that drive valves or other transducers which need to be off on power-up. the internal reference is initially powered down to allow use of an external reference. the MAX5800/max5801/ max5802 allow simultaneous output updates using soft - ware load commands. a clear logic input ( clr ) allows the contents of the code and the dac registers to be cleared asynchronously and sets the dac outputs to zero. the MAX5800/max5801/ max5802 are available in a small 10-pin max m and an ultra-small, 10-pin tdfn package and are specified over the -40 n c to +125 n c temperature range. applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation data acquisition benefits and features s two high-accuracy dac channels ? 12-bit accuracy without adjustment ? 1 lsb inl buffered voltage output ? monotonic over all operating conditions ? independent mode settings for each dac s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 4.5s settling time ? outputs directly drive 2k i loads s small 5mm x 3mm 10-pin max or ultra-small 3mm x 3mm 10-pin tdfn package s wide 2.7v to 5.5v supply range s separate 1.8v to 5.5v v ddio power-supply input s fast 400khz i 2 c-compatible, 2-wire serial interface s power-on-reset to zero-scale dac output s clr for asynchronous control s three software-selectable power-down output impedances ? 1k i , 100k i , or high impedance s low 350a supply current at 3v v dd 19-6461; rev 0; 9/12 ordering information appears at end of data sheet . functional diagram addr sda scl outa buffer por v dd gnd dac control logic power-down ref outb v ddio clr i 2 c serial interface 1ki 100ki code load clear/ reset clear / reset code register dac latch 8- /1 0- / 12-bit dac 1 of 2 dac channels internal reference/ external buffer MAX5800 max5801 max5802 for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5800.related max is a registered trademark of maxim integrated products, inc. MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v dd , v ddio to gnd ................................................ -0.3v to +6v out_, ref to gnd .................................... -0.3v to the lower of (v dd + 0.3v) and +6v scl, sda, clr to gnd .......................................... -0.3v to +6v addr to gnd ............................................. -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70 n c) max (derate at 8.8mw/ n c above 70 n c) .................... 707mw tdfn (derate at 24.4mw/ n c above 70 n c) ................ 1951mw maximum continuous current into any pin .................... q 50ma operating temperature range ........................ -40 n c to +125 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) .................................... +260 n c max junction-to-ambient thermal resistance ( ja ) ....... 113 n c/w junction-to-case thermal resistance ( jc ) .............. 42 n c/w tdfn junction-to-ambient thermal resistance ( ja ) .......... 41 n c/w junction-to-case thermal resistance ( jc ) ................ 9 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units dc performance (note 3) resolution and monotonicity n MAX5800 8 bits max5801 10 max5802 12 integral nonlinearity (note 4) inl MAX5800 -0.25 q 0.05 +0.25 lsb max5801 -0.5 q 0.25 +0.5 max5802 -1 q 0. 5 +1 differential nonlinearity (note 4) dnl MAX5800 -0.25 q 0.05 +0.25 lsb max5801 -0.5 q 0.1 +0.5 max5802 -1 q 0.2 +1 offset error (note 5) oe -5 q 0.5 +5 mv offset error drift q 10 f v/ n c gain error (note 5) ge -1.0 q 0.1 +1.0 %fs gain temperature coefficient with respect to v ref q 3.0 ppm of fs/ n c zero-scale error 0 10 mv full-scale error with respect to v ref -0.5 +0.5 %fs maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units dac output characteristics output voltage range (note 6) no load 0 v dd v 2k i load to gnd 0 v dd - 0.2 2k i load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 300 f v/ma v dd = 5v q 10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 0.3 i v dd = 5v q 10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 k i short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q 10% or 5v q 10% 100 f v/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/ f s voltage-output settling time ? scale to ? scale, to p 1 lsb, MAX5800 2.2 f s ? scale to ? scale, to p 1 lsb, max5801 2.6 ? scale to ? scale, to p 1 lsb, max5802 4.5 dac glitch impulse major code transition 7 nv*s channel-to-channel feedthrough (note 7) external reference 3.5 nv*s internal reference 3.3 digital feedthrough code = 0, all digital inputs from 0v to v ddio 0.2 nv*s power-up time startup calibration time (note 8) 200 f s from power-down 50 f s maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/ hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 f v p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/ hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 f v p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 f a reference input impedance r ref 75 100 k i reference ouput reference output voltage v ref v ref = 2.048v, t a = +25 n c 2.043 2.048 2.053 v v ref = 2.5v, t a = +25 n c 2.494 2.5 2.506 v ref = 4.096v, t a = +25 n c 4.086 4.096 4.106 reference output noise density v ref = 2.048v f = 1khz 129 nv/ hz f = 10khz 122 v ref = 2.500v f = 1khz 158 f = 10khz 151 v ref = 4.096v f = 1khz 254 f = 10khz 237 integrated reference output noise v ref = 2.048v f = 0.1hz to 10hz 12 v p-p f = 0.1hz to 10khz 110 f = 0.1hz to 300khz 390 v ref = 2.500v f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 129 f = 0.1hz to 300khz 430 v ref = 4.096v f = 0.1hz to 10hz 20 f = 0.1hz to 10khz 205 f = 0.1hz to 300khz 525 reference temperature coefficient (note 9) max5802a q 3.7 q 10 ppm/ n c MAX5800/max5801/max5802b q 10 q 25 reference drive capacity external load 25 k i reference capacitive load 200 pf reference load regulation i source = 0 to 500 f a 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v interface supply current (note 10) i ddio 1 f a maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units supply current (note 10) i dd internal reference v ref = 2.048v 0.55 0.75 ma v ref = 2.5v 0.60 0.80 v ref = 4.096v 0.65 0.90 external reference v ref = 3v 0.40 0.60 v ref = 5v 0.55 0.75 power-down mode supply current i pd both dacs off, internal reference on 140 f a both dacs off, internal reference off, t a = -40 n c to +85 n c 0.5 1 both dacs off, internal reference off, t a = +125 n c 1.2 2.5 digital input characteristics (scl, sda, addr, clr ) input high voltage v ih 2.2v < v ddio < 5.5v 0.7 x v ddio v 1.8v < v ddio < 2.2v 0.8 x v ddio v input low voltage v il 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio hysteresis voltage v h 0.15 v input leakage current i in v in = 0v or v ddio (note 10) q 0.1 q 1 f a input capacitance (note 10) c in 10 pf addr pullup/pulldown strength r pu , r pd (note 11) 30 50 90 k i digital output (sda) output low voltage v ol i sink = 3ma 0.2 v i 2 c timing characteristics (scl, sda, clr ) scl clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 f s hold time repeated for a start condition t hd;sta 0.6 f s scl pulse width low t low 1.3 f s scl pulse width high t high 0.6 f s setup time for repeated start condition t su;sta 0.6 f s data hold time t hd;dat 0 900 ns data setup time t su;dat 100 ns maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
7 figure 1. i 2 c serial interface timing diagram electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: limits are 100% production tested at t a = +25 n c and/or t a = +125 n c . limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are at t a = +25 n c and are not guaranteed. note 3: dc performance is tested without load. note 4: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 5: gain and offset calculated from measurements made with v ref = v dd at codes 30 and 4065 for max5802, codes 8 and 1016 for max5801, and codes 2 and 254 for MAX5800. note 6: subject to zero and full-scale error limits and v ref settings. note 7: measured with the dac outputs at midscale with one channel transitioning 0 to full scale. note 8: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 9: guaranteed by design. note 10: both channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v ddio . note 11: an unconnected condition on the addr pin is sensed via a resistive pullup and pulldown operation; for proper operation, the addr pin should be tied to v ddio , gnd, or left unconnected with minimal capacitance. parameter symbol conditions min typ max units sda and scl receiving rise time t r 20 + c b /10 300 ns sda and scl receiving fall time t f 20 + c b /10 300 ns sda transmitting fall time t f 20 + c b /10 250 ns setup time for stop condition t su;sto 0.6 f s bus capacitance allowed c b v dd = 2.7v to 5.5v 10 400 pf pulse width of suppressed spike t sp 50 ns clr removal time prior to a recognized start t clrsta 100 ns clr pulse width low t clpw 20 ns t su;sto t r t sp t hd;sta t su;sta t f t high t hd;dat t low t clpw t clrsta t hd;sta t f s s s r p sd a sc l cl r t su;dat t r t buf maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
8 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface typical operating characteristics (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) dnl vs. code MAX5800 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage MAX5800 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v ref = 3v 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature MAX5800 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl inl vs. code MAX5800 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code MAX5800 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code MAX5800 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load
9 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface typical operating characteristics (continued) (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) offset and zero-scale error vs. supply voltage MAX5800 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load offset and zero-scale error vs. temperature MAX5800 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain error vs. supply voltage MAX5800 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error full-scale error and gain error vs. temperature MAX5800 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature MAX5800 toc11 temperature (c) supply current (ma) 110 95 -25 -10 5 35 50 65 20 80 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 -40 125 out_ = full scale no load v ref (external) = v dd = 3v v ref (external) = v dd = 5v v ref (internal) = 4.096v, v dd = 5v v ref (internal) = 2.5v, v dd = 5v v ref (internal) = 2.048v, v dd = 5v supply current vs. supply voltage \MAX5800 toc12 v dd (v) supply current (ma) 5.2 4.7 3.2 3.7 4.2 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.30 2.7 v ref = 4.096v (internal) v ref = 2.500v (internal) v ref = 2.048v (internal) v ref = 2.5v (external)
10 typical operating characteristics (continued) (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) power-down mode supply current vs. temperature MAX5800 toc13 supply voltage (v) 5.1 3.5 3.9 4.3 4.7 3.1 2.7 5.5 power-down supply current (a) 0.4 0.8 1.6 1.2 0 power-down mode all dacs t a = -40c t a = +25c t a = +85c t a = +125c supply current vs. code MAX5800 toc14 code (lsb) supply current (ma) 3584 3072 2560 2048 1536 1024 512 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.10 0 4096 v dd = 5v v ref = 4.096v v dd = 5v v ref = 2.500v v dd = 5v v ref = 5.0v (external) v dd = 3v v ref = 3.0v (external) v dd = 5v v ref = 2.048v i ref (external) vs. code MAX5800 toc15 code (lsb) reference current ( a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v MAX5800 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div 4.3s settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scal e MAX5800 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scal e major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) MAX5800 toc18 v out 3.3mv/div trigger pulse 5v/div 1 lsb change (midcode transition from 0x7ff to 0x800) glitch energy = 6.7nv*s maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
11 typical operating characteristics (continued) (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) major code transition glitch energy (v dd = v ref = 5v, r l = 2ki, c l = 200pf) MAX5800 toc19 v out 3.3mv/div trigger pulse 5v/div 1 lsb change (midcode transition from 0x800 to 0x7ff) glitch energy = 6nv*s 2s/div v out vs. time transient exiting power-down MAX5800 toc20 dac output 500mv/div 10s / div v scl 5v/div 0v 0v v dd = 5v, v ref = 2.5v external 36th edge power-on reset to 0v MAX5800 toc21 v out 2v/div 20s / div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) MAX5800 toc23 5s / div no load no load trigger pulse 10v/div static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.8nv*s channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) MAX5800 toc22 4s / div trigger pulse 10v/div transitioning dac 1v/div r l = 2k i no load static dac 1.25mv/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.5nv*s channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) MAX5800 toc24 5s / div trigger pulse 10v/div no load static dac 1.25mv/div transitioning dac 1v/div transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s r l = 2k i maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
12 MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface typical operating characteristics (continued) (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) MAX5800 toc25 trigger pulse 10v/div transitioning dac 1v/div static dac 1.25mv/div no load no load 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, no load) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 1.1nv*s MAX5800 toc26 40ns/div digital feedthrough (v dd = v ref = 5v, r l = 2ki , c l = 200pf) v dd = 5v v re f = 5v (external) dacs at midscale v ou t 1.65mv/div digital feedthrough = 0.1nvs output load regulation MAX5800 toc27 i o ut (ma) d v out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v headroom at rails vs. output current MAX5800 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking v dd = v ref dac = zero scale v dd = v ref dac = full scale output current limiting MAX5800 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v noise-voltage density vs. frequency (dac at midscale) MAX5800 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.048v (internal) v dd = 5v, v ref = 4.5v (external) v dd = 5v, v ref = 4.096v (internal) v dd = 5v, v ref = 2.5v (internal) maxim integrated
13 typical operating characteristics (continued) (max5802, 12-bit performance, t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) MAX5800 toc31 2v/div midscale unloaded v p-p = 12v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) MAX5800 toc32 2v/div midscale unloaded v p-p = 13v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) MAX5800 toc33 2v/div midscale unloaded v p-p = 15v 4s /div v ref drift vs. temperature MAX5800 toc35 temperature drift (ppm /c) percent of population (%) 4.3 4.1 4.0 3.9 3.7 3.6 3.4 3.3 3.2 3.0 2.9 5 10 15 20 25 0 0.2 4.4 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) MAX5800 toc34 2v/div midscale unloaded v p-p = 16v 4s /div reference load regulation MAX5800 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v dd = 5v internal reference v ref = 2.048v, 2.5v, and 4.096v supply current vs. input logic voltage MAX5800 toc37 input logic voltage (v) supply current (a) 4 3 2 1 200 400 600 800 1000 1200 1400 1600 1800 2000 0 05 v ddio = 5v v ddio = 3v v ddio = 1.8v typical operating characteristics (t a = +25c, unless otherwise noted.) maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
14 pin description pin configurations pin name function 1 ref reference voltage input/output 2 outa buffered channel a dac output 3 outb buffered channel b dac output 4 gnd ground 5 v dd supply voltage input. bypass v dd with at least a 0.1 f f capacitor to gnd. 6 addr i 2 c interface address selection bit 7 scl i 2 c interface clock input 8 sda i 2 c bidirectional serial data 9 v ddio digital interface power-supply input 10 clr active-low clear input ep exposed pad (tdfn only). connect to ground. top view 1 3 4 10 8 7 clr sda scl MAX5800 max5801 max5802 2 9 v ddio 5 + 6 addr ref outb gnd outa v dd ep tdfn 1 2 3 4 5 10 9 8 7 6 v ddio sda scl gnd outb outa ref MAX5800 max5801 max5802 max addr v dd clr + maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
15 detailed description the MAX5800/max5801/max5802 are 2-channel, low- power, 8-/10-/12-bit buffered voltage-output dacs. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommodates most low-power and low- voltage applications. the devices present a 100k i load to the external reference. the internal output buffers allow rail-to-rail operation. an internal voltage reference is available with software selectable options of 2.048v, 2.5v, or 4.096v. the devices feature a fast 400khz i 2 c- compatible interface. the MAX5800/max5801/max5802 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) cir - cuit to initialize the dac outputs to code zero, and con - trol logic. clr is available to asynchronously clear the device independent of the serial interface. dac outputs (out_) the MAX5800/max5801/max5802 include internal buf - fers on both dac outputs. the internal output buffers provide improved load regulation for the dac outputs. the output buffers slew at 1v/ f s (typ) and drive up to 2k i in parallel with 500pf. the analog supply voltage (v dd ) determines the maximum output voltage range of the devices as v dd powers the output buffer. under no-load conditions, the output buffers drive from gnd to v dd , subject to offset and gain errors. with a 2k load to gnd, the output buffers drive from gnd to within 200mv of v dd . with a 2k load to v dd , the output buffers drive from v dd to within 200mv of gnd. the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple dacs as determined by the user command. within each dac channel there is a code register followed by a dac latch register (see the detailed functional diagram ). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user com - mands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands. the contents of both code and dac registers are main - tained during power-down states, so that when the dacs are powered on, they return to their previously stored output settings. any code or load commands issued during power-down states continue to update the register contents. sw_clear and sw_reset commands reset the contents of all code and dac registers to their zero- scale defaults. internal reference the MAX5800/max5801/max5802 include an internal precision voltage reference that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal refer - ence is selected, that voltage is available on the ref pin for other external circuitry (see the typical operating circuits ) and can drive a 25k i load. external reference the external reference input has a typical input impedance of 100k i and accepts an input voltage from +1.24v to v dd . connect an external voltage supply between ref and gnd to apply an exter - nal reference. the MAX5800/max5801/max5802 power up and reset to external reference mode. visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. clear input ( clr ) the MAX5800/max5801/max5802 feature an asynchro - nous active-low clr logic input that simultaneously sets both dac outputs to zero. driving clr low clears the contents of both the code and dac registers and also aborts the on-going i 2 c command. to allow a new i 2 c command, drive clr high, satisfying the t clrsta timing requirement. interface power supply (v ddio ) the MAX5800/max5801/max5802 feature a separate supply pin (v ddio ) for the digital interface (1.8v to 5.5v). connect v ddio to the i/o supply of the host processor. maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
16 i 2 c serial interface the MAX5800/max5801/max5802 feature an i 2 c-/ smbus k -compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl enable communication between the MAX5800/ max5801/max5802 and the master at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the MAX5800/max5801/max5802 by transmitting the proper slave address followed by the command byte and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the MAX5800/ max5801/max5802 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX5800/max5801/max5802 must transmit the proper slave address followed by a series of nine scl pulses for each byte of data requested. the MAX5800/ max5801/max5802 transmit data on sda in sync with the master-generated scl pulses. the master acknowl - edges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typically 4.7k i is required on sda. scl oper - ates only as an input. a pullup resistor, typically 4.7k i , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX5800/ max5801/max5802 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. the MAX5800/max5801/max5802 can accom - modate bus voltages higher than v ddio up to a limit of 5.5v; bus voltages lower than v ddio are not recommend - ed and may result in significantly increased interface cur - rents. the MAX5800/max5801/max5802 digital inputs are double buffered. depending on the command issued through the serial interface, the code register(s) can be loaded without affecting the dac register(s) using the write command. to update the dac registers, use the software load command. i 2 c start and stop conditions sda and scl idle high when the bus is not in use. a mas - ter initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high ( figure 2 ). a start condition from the master signals the beginning of a transmission to the MAX5800/max5801/max5802. the master termi - nates transmission and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. i 2 c early stop and repeated start conditions the MAX5800/max5801/max5802 recognize a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. transmissions ending in an early stop condition will not impact the internal device set - tings. if the stop occurs during a readback byte, the transmission is terminated and a later read mode request will begin transfer of the requested register data from the beginning (this applies to combined format i 2 c read mode transfers only, interface verification mode transfers will be corrupted). see figure 2 . figure 2. i 2 c start, repeated start, and stop conditions smbus is a trademark of intel corp. figure 2 scl sda ss rp valid start, repeated start, and stop pulses ps p sp p s invalid start/s top pulse pairings -all will be recognized as starts maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
17 i 2 c slave address the slave address is defined as the seven most sig - nificant bits (msbs) followed by the r/ w bit. see figure 4 . the five most significant bits are 00011 with the 2 lsbs determined by addr as shown in table 1 . setting the r/ w bit to 1 configures the MAX5800/max5801/ max5802 for read mode. setting the r/ w bit to 0 config - ures the MAX5800/max5801/max5802 for write mode. the slave address is the first byte of information sent to the MAX5800/max5801/max5802 after the start condition. the MAX5800/max5801/max5802 have the ability to detect an unconnected state on the addr input for additional address flexibility; if leaving the addr input unconnected, be certain to minimize all loading on the pin (i.e. provide a landing for the pin, but do not allow any board traces). i 2 c broadcast address a broadcast address is provided for the purpose of updating or configuring all MAX5800/max5801/max5802 devices on a given i 2 c bus. all MAX5800/max5801/ max5802 devices acknowledge and respond to the broadcast device address 00010000. the devices will respond to the broadcast address, regardless of the state of the address pins. the broadcast mode is intend - ed for use in write mode only (as indicated by r/ w = 0 in the address given). i 2 c acknowledge in write mode, the acknowledge bit (ack) is a clocked 9th bit that the MAX5800/max5801/max5802 use to hand - shake receipt of each byte of data as shown in figure 3 . the MAX5800/max5801/max5802 pull down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccess - ful data transfer, the bus master will retry communication. figure 3. i 2 c acknowledge table 1. i 2 c slave address lsbs figure 4. i 2 c single register write sequence a[6:2] = 00011 addr a1 a0 v ddio 0 0 n.c. 1 0 gnd 1 1 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) 21 22 23 stop 7 6 5 4 3 2 1 a 0 ack. generated by MAX5800/ max5801/ max5802 command executed 1 1 a1 a0 0 0 0 a maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
18 in read mode, the master pulls down sda during the 9th clock cycle to acknowledge receipt of data from the MAX5800/max5801/max5802. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not-acknowledge is sent when the master reads the final byte of data from the MAX5800/max5801/ max5802, followed by a stop condition. i 2 c command byte and data bytes a command byte follows the slave address. a command byte is typically followed by two data bytes unless it is the last byte in the transmission. if data bytes follow the command byte, the command byte indicates the address of the register that is to receive the following two data bytes. the data bytes are stored in a temporary register and then transferred to the appropriate register during the ack periods between bytes. this avoids any glitch - ing or digital feedthrough to the dacs while the interface is active. i 2 c write operations a master device communicates with the MAX5800/ max5801/max5802 by transmitting the proper slave address followed by command and data words. each transmit sequence is framed by a start or repeated start condition and a stop condition as described above. each word is 8 bits long and is always followed by an acknowledge clock (ack) pulse as shown in the figure 4 and figure 5 . the first byte contains the address of the MAX5800/max5801/max5802 with r/ w = 0 to indicate a write. the second byte contains the register (or com - mand) to be written and the third and fourth bytes contain the data to be written. by repeating the register address plus data pairs (byte #2 through byte #4 in figure 4 and figure 5 ), the user can perform multiple register writes using a single i 2 c command sequence. there is no limit as to how many registers the user can write with a single command. the MAX5800/max5801/max5802 support this capability for all user-accessible write mode commands. combined format i 2 c readback operations each readback sequence is framed by a start or repeated start condition and a stop condition. each word is 8 bits long and is followed by an acknowledge clock pulse as shown in figure 6 . the first byte contains the address of the MAX5800/max5801/max5802 with r/ w = 0 to indicate a write. the second byte contains the register that is to be read back. there is a repeated start condition, followed by the device address with r/ w = 1 to indicate a read and an acknowledge clock. the master has control of the scl line but the MAX5800/ max5801/max5802 take over the sda line. the final two bytes in the frame contain the register data readback followed by a stop condition. if additional bytes beyond those required to readback the requested data are pro - vided, the MAX5800/max5801/max5802 will continue to readback ones. readback of individual code registers is supported for the code command (b[23:20] = 0000). for this com - mand, which supports a dac address, the requested figure 5. multiple register write sequence (standard i 2 c protocol) scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command1 byte #2: command1 byte (b[23:16]) write data1 byte #3: data1 high byte (b[15:8]) 21 0 0 0 1 1 a1 a0 22 23 stop 7 6 5 4 3 2 1a 0 write data1 byte #4: data1 low byte (b[7:0]) 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 21 22 23 7 6 5 4 3 2 1a 0 additional command and data pairs (3 byte blocks) command1 executed commandn executed byte #5: commandn byte (b[23:16]) byte #6: datan high byt e (b[15:8]) byte #7: datan low byt e (b[7:0]) ack. generated by MAX5800/ max5801/ max5802 a maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
19 figure 6. standard i 2 c register read sequence channel code register content will be returned; if both dacs are selected, codea content will be returned. readback of individual dac registers is supported for all load commands (b[23:20] = 0001, 0010, or 0011). for these commands, which support a dac address, the requested dac register content will be returned. if both dacs are selected, daca content will be returned. modified readback of the power register is supported for the power command (b[23:20] = 0100). the power status of each dac is reported in locations b[1:0], with a 1 indicating the dac is powered down and a 0 indicating the dac is operational (see table 2 ). readback of all other registers is not directly supported. all requests to read unsupported registers reads back the devices reference status and the device id and revi - sion information in the format as shown in table 2 . interface verification i 2 c readback operations while the MAX5800/max5801/max5802 support stan - dard i 2 c readback of selected registers, it is also capable of functioning in an interface verification mode. this mode is accessed any time a readback operation follows an executed write mode command. in this mode, the last executed three-byte command is read back in its entirety. this behavior allows verification of the interface. sample command sequences are shown in figure 7 . the first command transfer is given in write mode with r/ w = 0 and must be run to completion to qualify for interface verification readback. there is now a stop/ start pair or repeated start condition required, fol - lowed by the readback transfer with r/ w = 1 to indicate a read and an acknowledge clock from the MAX5800/ max5801/max5802. the master still has control of the table 2. standard i 2 c user readback data command byte (request) readback data high byte readback data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 dac selection coden[11:4] coden[3:0] 0 0 0 0 0 0 0 1 dac selection dacn[11:4] dacn[3:0] 0 0 0 0 0 0 1 0 dac selection dacn[11:4] dacn[3:0] 0 0 0 0 0 0 1 1 dac selection dacn[11:4] dacn[3:0] 0 0 0 0 0 1 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pwb pwa 1 0 0 0 0 0 0 0 codea[11:4] codea[3:0] 0 0 0 0 1 0 0 0 0 0 0 1 daca[11:4] daca[3:0] 0 0 0 0 1 0 1 0 0 0 1 0 daca[11:4] daca[3:0] 0 0 0 0 1 0 1 1 0 0 1 1 daca[11:4] daca[3:0] 0 0 0 0 any other command 1001 1000 000 rev_id[2:0] (011) ref mode rf[1:0] read data byte #4: data 1 high byte (b[15:8]) read data byte #5: data 1 low byte (b[7:0]) repeated start read address byte #3: i 2 c slave address write address byte #1: i 2 c slave address write command 1 byte #2: command 1 byte ack. generated by MAX5800/ max5801/ max5802 ack. generated by i 2 c master a start stop scl sda 00 01 1a 1a 0w a a a n nn 0 00 11 a1 a0 ra d ddd dd dd dddddddd ~a a nn nnn maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
20 figure 7. interface verification i 2 c register read sequences scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9 a 8 sda 0 0 0 1 1 a1 a0 22 23 7 6 5 4 3 2 1 a 0 r ~a pointer updated (qualifies for combined read back) command executed (qualifies for interface read back) scl sda command executed (qualifies for interface read back) pointer updated (qualifies for combined read back) 21 a w2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 1a 0 21 start stop write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) start stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) start repeated start write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) ack. generated by MAX5800/max5801/max5802 ack. generated by i 2 c master a2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 10 21 a r2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 01 1a 1a 02 2 23 76 54 32 1~ a 0 21 a a maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
21 scl line but the MAX5800/max5801/max5802 take over the sda line. the final three bytes in the frame contain the command and register data written in the first transfer presented for readback, followed by a stop condition. if additional bytes beyond those required to read back the requested data are provided, the MAX5800/max5801/ max5802 will continue to read back ones. it is not necessary for the write and read mode transfers to occur immediately in sequence. i 2 c transfers involv - ing other devices do not impact the MAX5800/max5801/ max5802 readback mode. toggling between readback modes is based on the length of the preceding write mode transfer. combined format i 2 c readback operation is resumed if a write command greater than two bytes but less than four bytes is supplied. for commands writ - ten using multiple register write sequences, only the last command executed is read back. for each command written, the readback sequence can only be completed one time; partial and/or multiple attempts to readback executed in succession will not yield usable data. i 2 c compatibility the MAX5800/max5801/max5802 are fully compatible with existing i 2 c systems. scl and sda are high-imped - ance inputs; sda has an open drain which pulls the data line low to transmit data or ack pulses. figure 8 shows a typical i 2 c application. i 2 c user-command register map this section lists the user accessible commands and registers for the MAX5800/max5801/max5802. each serial operation word is 24-bits long. the dac data is left justified as shown in table 3. table 4 provides detailed information about the command registers. table 3. format dac data bit positions figure 8. typical i 2 c application circuit part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MAX5800 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5801 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x max5802 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c addr scl sda scl sda addr +5v scl sda MAX5800 max5801 max5802 MAX5800 max5801 max5802 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
22 table 4. i 2 c commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description dac commands coden 0 0 0 0 dac selection code register data[11:4] code register data[3:0] x x x x writes data to the selected code register(s) loadn 0 0 0 1 dac selection x x x x x x x x x x x x x x x x transfers data from the selected code register(s) to the selected dac register(s) coden_ load_all 0 0 1 0 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers coden_ loadn 0 0 1 1 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) configuration commands power 0 1 0 0 0 0 power mode 00 = normal 01 = pd 1k i 10 = pd 100k i 11 = pd hi-z x x x x x x dac b dac a x x x x x x x x sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) sw_clear 0 1 0 1 0 0 0 0 x x x x x x x x x x x x x x x x executes a software clear (all code and dac registers cleared to their default values) sw_reset 0 1 0 1 0 0 0 1 x x x x x x x x x x x x x x x x executes a software reset (all code, dac, and control registers returned to their default values) maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
23 table 4. i 2 c commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description config 0 1 1 0 0 0 0 ld_en x x x x x x dac b dac a x x x x x x x x sets the dac latch mode of the selected dacs. only dacs with a 1 in the selection bit are updated by the command. ld_en = 0: dac latch is operational (load controlled) ld_en = 1: dac latch is transparent ref 0 1 1 1 0 ref power 0 = dac 1 = on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x x sets the reference operating mode. ref power (b18): 0 = internal reference is only powered if at least one dac is powered 1 = internal reference is always powered all dac commands code_all 1 0 0 0 0 0 0 0 code register data[11:4] code register data[3:0] x x x x writes data to all code registers load_all 1 0 0 0 0 0 0 1 x x x x x x x x x x x x x x x x updates all dac latches with current code register data code_ all_ load_all 1 0 0 0 0 0 1 x code register data[11:4] code register data[3:0] x x x x simultaneously writes data to all code registers while updating all dac registers no operation commands no operation 1 0 0 1 x x x x x x x x x x x x x x x x x x x x these commands will have no effect on the device 1 0 1 x x x x x x x x x x x x x x x x x x x x x 1 1 x x x x x x x x x x x x x x x x x x x x x x reserved commands : any commands not specifically listed above are reserved for maxim internal use only. maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
24 table 5. dac selection b19 b18 b17 b16 dac selected 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 x no effect x 1 x x all dacs 1 x x x all dacs coden command the coden command (b[23:20] = 0000) updates the code register contents for the selected dac(s). changes to the code register content based on this command will not affect dac outputs directly unless the dac latch has been configured to be transparent. issuing the coden command with dac selection = all dacs is equiva - lent to code_all (b[23:16] = 10000000). see table 4 and table 5 . loadn command the loadn command (b[23:20] = 0001) updates the dac register content for the selected dac(s) by upload - ing the current contents of the code register. the loadn command can be used with dac selection = all dacs to issue a software load for both dacs, which is equivalent to the load_all (b[23:16] = 10000001) command. see table 4 and table 5 . coden_load_all command the coden_load_all command (b[23:20] = 0010) updates the code register contents for the selected dac(s) as well as the dac register content of both dacs. channels for which the code register content has not been modified since the last load to dac register operation will not be updated to reduce digital crosstalk. issuing this command with dac_address = all is equivalent to the code_all_load_all command. the coden_load_all command by definition will modify at least one code register. to avoid this, use the loadn command with dac selection = all dacs or use the load_all command. see table 4 and table 5 . coden_loadn command the coden_loadn command (b[23:20] = 0011) updates the code register contents for the selected dac(s) as well as the dac register content of the selected dac(s). channels for which the code register content has not been modified since the last load to dac register operation will not be updated to reduce digital crosstalk. issuing this command with dac selection = all dacs is equivalent to the code_all_load_all command. see table 4 and table 5 . code_all command the code_all command (b[23:16] = 10000000) updates the code register contents for both dacs. see table 4 . load_all command the load_all command (b[23:16] = 10000001) updates the dac register content for both dacs by uploading the current contents of the code registers. see table 4 . code_all_load_all command the code_all_load_all command (b[23:16] = 1000001x) updates the code register contents for both dacs as well as the dac register content of both dacs. see table 4 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
25 power command the MAX5800/max5801/max5802 feature a software- controlled power-mode (power) command (b[23:18] = 010000). the power command updates the power- mode settings of the selected dacs while the power set - tings of the rest of the dacs remain unchanged. the new power setting is determined by bits b[17:16] while the affected dac(s) are selected by bits b[9:8]. if all dacs are powered down, the device enters a standby mode. in power-down, the dac output is disconnected from the buffer and is grounded with either one of the two selectable internal resistors or set to high impedance. see table 7 for the selectable internal resistor values in power-down mode. in power-down mode, t he dac register retains its value so that the output is restored when the device powers up. the serial interface remains active in power-down mode. in standby mode, the internal reference can be pow - ered down or it can be set to remain powered-on for external use. also, in standby mode, devices using the external reference do not load the ref pin. see table 6 . sw_reset and sw_clear command the sw_reset (b[23:16] = 01010001) and sw_clear (b[23:16] = 01010000) commands provide a means of issuing a software reset or software clear operation. use sw_clear to issue a software clear operation to return all code and dac registers to the zero-scale value. use sw_reset to reset all code, dac, and configuration registers to their default values. table 6. power command format table 7. selectable dac output impedance in power-down mode pd1 (b17) pd0 (b16) operating mode 0 0 normal operation 0 1 power-down with internal 1k i pulldown resistor to gnd. 1 0 power-down with internal 100k i pulldown resistor to gnd. 1 1 power-down with high-impedance output. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 0 pd1 pd0 x x x x x x b a x x x x x x x x power command power mode: 00 = normal 01 = 1k i 10 = 100k i 11 = hi-z dont care dac select: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 0 x x x x x x 1 1 x x x x x x x x maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
26 config command the config command (b[23:17] = 0110000) updates the load functions of selected dacs. issue the com - mand with b16 = 0 to allow the dac latches to operate normally or with b16 = 1 to disable the dac latches, making them perpetually transparent. mode settings of the selected dacs are updated while the mode settings of the rest of the dacs remain unchanged; dac(s) are selected by bits b[9:8]. see table 8 . ref command the ref command (b[23:19] = 01110) updates the global reference setting used for both dac channels. set b[17:16] = 00 to use an external reference for the dacs or set b[17:16] to 01, 10, or 11 to select either the 2.5v, 2.048v, or 4.096v internal reference, respectively. if rf2 (b18) is set to zero (default) in the ref command, the reference will be powered down any time both dac channels are powered down (in standby mode). if rf2 (b18 = 1) is set to one, the reference will remain powered even if both dac channels are powered down, allowing continued operation of external circuitry. in this mode, the 1 f a shutdown state is not available. see table 9 . table 8. config command format table 9. ref command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 0 0 0 ldb x x x x x x b a x x x x x x x x config command 0 = normal 1 = transparent dont care dac select: 1 = dac selected 0 = dac not selected dont care default values (all dacs) ? 0 x x x x x x 1 1 x x x x x x x x b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 0 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command 0 = off in standby 1 = on in standby ref mode: 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.0v dont care dont care default values ? 0 0 0 x x x x x x x x x x x x x x x x maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
27 applications information power-on reset (por) when power is applied to v dd and v ddio , the dac out - put is set to zero scale. to optimize dac linearity, wait until the supplies have settled and the internal setup and calibration sequence completes (200 f s, typ). power supplies and bypassing considerations bypass v dd and v ddio with high-quality ceramic capac - itors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead induc - tance. connect the gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5800/max5801/max5802 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire-wrapped boards and sockets. use shielding to minimize noise immu - nity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the MAX5800/max5801/max5802 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer function matches the ideal transfer function. the offset error is calculated from two measurements near zero code and near maximum code. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. zero-scale error zero-scale error is the difference between the dac output voltage when set to code zero and ground. this includes offset and other die level nonidealities. full-scale error full-scale error is the difference between the dac output voltage when set to full scale and the reference voltage. this includes offset, gain error, and other die level non- idealities. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
28 detailed functional diagram outa buffer a dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register a dac latch a 8- /1 0- /1 2- bit dac a outb buffer b dac control logic power-down 1ki 100ki code load clear / reset clear / reset code register b dac latch b 8- /1 0- /1 2- bit dac b addr sda scl v ddio por clr i 2 c serial interface ref 100ki r in internal/ external reference (user option) MAX5800 max5801 max5802 v dd gnd maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
29 typical operating circuits dac micro- controller sda scl addr out_ gnd v ddio v dd clr note: unipolar operation (one channel shown) ref 100nf 100nf 4.7f r pu = 5ki r pu = 5ki MAX5800 max5801 max5802 v out = 0v to v ref dac micro- controller sda scl addr out gnd v ddio v dd clr note: bipolar operation (one channel shown) ref 100nf 100nf 4.7f r pu = 5ki r pu = 5ki r1 r2 r1 = r2 MAX5800 max5801 max5802 v out = -v ref to +v ref maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
30 ordering information note: all devices are specified over the -40c to +125c temperature range. +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *future productcontact factory for availability. **ep = exposed pad. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part pin-package resolution (bit) internal reference tempco (ppm/ n c) MAX5800 atb+t* 10 tdfn-ep** 8 10 (typ), 25 (max) MAX5800aub+t* 10 max 8 10 (typ), 25 (max) max5801 atb+t* 10 tdfn-ep** 10 10 (typ), 25 (max) max5801aub+t* 10 max 10 10 (typ), 25 (max) max5802 aatb+t* 10 tdfn-ep** 12 3 (typ), 10 (max) max5802aaub+t 10 max 12 3 (typ), 10 (max) max5802batb+t* 10 tdfn-ep** 12 10 (typ), 25 (max) max5802baub+t* 10 max 12 10 (typ), 25 (max) package type package code outline no. land pattern no. 10 max u10+2 21-0061 90-0330 10 tdfn-ep t1033+1 21-0137 90-0003 maxim integrated MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 31 ? 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/12 initial release MAX5800/max5801/max5802 ultra-small, dual-channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface

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